The compilation time is too long for Intel FPGA OpenCL
I am trying to compile a HLS project with Intel SDK for OpenCL 20.3 on DE10 PRO. This project used to take 5~6 hours to compile on Intel SDK for OpenCL 19.4 on Arria10, but it has taken more than 17 hours of compilation now. The resource consumption in Linux is shown below. It seems that the resource used is not that much. The latest file generated in compilation is shown below. It seems that routing has been finished successfully. But after top.fit.route.rpt generated, 5 hours has been consumed with no refresh in any file. I want to know if it is usual to take such a long time in compilation and how can I reduce the compilation time in this flow.
Intel OpenCL compiler (aoc) does not coalesce global memory reads anymore
The two screenshots says it all. The old screenshot is generated with aoc 21.2.0. Note how it coalesces the 16 float reads into one 512 bit DDR read. The new screenshot is generated with aoc 2024.2.1. It does not coalesce the 16 float reads and instead creates 16 individual read ports. Afaict, that is quite bad for performance and it wastes a lot of hardware resources. Is there a way to make aoc 2024.2.1 coalesce, exactly like the old compiler did?
Choosing FPGA board for ML implementation using oneAPI
Hello, I wish to implement transformer modules on an Intel FPGA using oneAPI. HBM is preferred and the compatability with oneAPI workflow is important. Some options I checked were: - Stratix 10 NX - Stratix 10 MX I did not find much about using the AI tensor blocks with oneAPI so wanted to check if there are no restrictions on that perspective. Other suggestions for the FPGA boards will be great too. Thanks
Valid substitute to EN5396QI-T
Goodmorning everyone, I am trying to find valid alternative to EN5396QI-T, EN5366QI and EN5337QI-T, which are now obsolete. I must ensure both the same output current, switching frequency and low input voltage. The substitute must have the integrated inductor too. Do you know any valid alternatives? At the moment, the best I found are the MPS DC-DC converters, but unfortunately they do not reach 5MHz of switching frequency. Thank you all for the attention, Best regards, Andrea B.
Why does aoc set ii to 6 when I use high clock frequencies?
I have a simple toy that I want to run at 1000 MHz kernel that doesn't do much: __attribute__((uses_global_work_offset(0))) __attribute__((max_global_work_dim(0))) __kernel void netsim( __global const volatile float * restrict gl_vm ) { float vm[50000]; #pragma ii 1 #pragma ivdep #pragma speculated_iterations 64 for (int i = 0; i < 50000; i++) { vm[i] = gl_vm[i]; } } According to the report (see screenshot), II=6 and latency=927. Why can't the compiler lower the latency and set II to 1 here?
