Can the new Intel® eASIC™ devices help you reach your 4G and 5G equipment design goals?
By Ronnie Vasishsta, VP and GM, Intel Corporation There is a lot of discussion in the industry today surrounding 5G telecommunications and networking. I even see television commercials about 5G popping up more and more. What's lost in all the excitement about 5G is that the 4G and 4G Advanced Pro standards are still in the deployment phase – and the equipment is still evolving. Many current telecom and networking use cases can be met with these existing 4G solutions and they serve as a bridge to 5G. As a result, vendors are now developing flexible equipment that can implement 4G standards now, with an eye towards reconfiguring them to 5G later. What 5G adds is not just new technologies but also new business models. Yes, 5G offers enhanced speed on mobile broadband, but the 5G technologies also add some new use cases. For example, some of these new use cases take advantage of new 5G capabilities such as massive machine-to-machine communications that are being used to facilitate smart factories, autonomous driving, enhanced video analytics, more accurate location tracking and a plethora of others. So 5G brings new capabilities, new use cases, and enhanced speed to the networking and telecom markets. Because these generational transitions from 4G to 5G are happening so quickly, and because 4G itself is evolving with new technologies such as massive MIMO, millimeter wave, beamforming, and carrier aggregation, it’s very hard for 4G and 5G equipment vendors to work with a fixed set of hardware solutions. Equipment vendors’ customers are looking for adaptable, configurable solutions to meet the changing needs of their customers. These solutions often must not only be software-configurable; they must take advantage of configurable hardware – meaning reconfigurable silicon – to meet some of the new technology latency, performance, power and cost requirements of these increasingly advanced networks. Intel is ideally situated to aid equipment vendors and their customers with this transformation as various 4G deployments and 5G standards are released. Intel software- and hardware-programmable products allow customers to accommodate the constant need for network reconfiguration while still maintaining performance, power, and cost targets. For these 4G and 5G applications, Intel® Xeon® CPUs, Intel® FPGAs, Intel® eASIC™ devices, and Intel® ASICs are very complementary products. Intel FPGAs can very efficiently implement certain functions within specific telecom and networking standards while offering benefits in terms of performance and cost. These FPGAs give equipment makers the option to quickly accelerate network functionality to an Intel FPGA sitting immediately adjacent to the Intel Xeon CPU. This migration option is especially attractive when Intel Xeon CPU cycles can better be used for revenue-generating tasks rather than for lower-level tasks. More efficiencies can be gained by moving the offloaded functions from the Intel FPGA to an Intel eASIC structured ASIC as designs mature and as feature sets solidify. Intel eASIC devices allow reuse of IP from FPGA-based designs and can cut power consumption by as much as 50% at the same clock frequency relative to the same designs implemented in FPGAs while also lowering unit costs. In addition, developing a design using an Intel eASIC device requires only half of the time needed to develop an ASIC with similar capabilities. The broad offering of Intel Xeon CPUs, Intel FPGAs, Intel eASIC devices, and Intel ASICs really gives equipment vendors the ability to carefully manage their product life cycles as their designs pass through various product phases from prototypes, to early production, to mature production volumes. Intel has introduced the next generation of Intel eASIC devices, code-named Diamond Mesa. These new Intel eASIC Diamond Mesa devices will consume less power and will be faster than the existing Intel eASIC N3XS products. In addition, these new Intel eASIC Diamond Mesa devices incorporate a multicore, embedded, hard processor subsystem, which means that these devices can implement control functions as well as well as many DSP and networking functions on a single device. The hard processor subsystem incorporated into the Intel eASIC Diamond Mesa devices allows the identical software to operate on both the new Intel® Agilex™ SoCs and the Intel eASIC Diamond Mesa devices. Structured ASICs like Diamond Mesa balance the configurability and fast time-to-market of FPGAs with the power-efficient, purpose-built performance of custom ASICs, and are a key piece of Intel’s 5G solution portfolio. Software and hardware portability across devices is a hallmark of Intel FPGAs and Intel eASIC devices. Significant know-how developed over many years permits Intel to migrate FPGA-based designs into an Intel eASIC structured ASIC quickly and easily while reusing much of the IP. In addition, Intel is moving some of the migration work to automated tools, which makes the process even faster and easier. However, your design need not target an Intel FPGA for easy migration to an Intel eASIC device. Intel has developed techniques to migrate designs from any vendor’s FPGA into Intel eASIC structured ASICs. Some customers that are familiar with Intel eASIC structured ASIC devices already target these devices directly for specific end products without ever targeting an FPGA. (Or, perhaps the FPGA is used for prototyping, in preparation for a conversion to an Intel eASIC device.) In such cases, a tool flow called eTools, which combines several in-house hardware development tools created by Intel, eases migration and helps customers implement their designs directly in the Intel eASIC fabric. It’s also possible to migrate from an eASIC device to a full-mask-set ASIC should the project’s power or unit-cost goals require it. Networking and telecom equipment OEMs and companies building out 4G and 5G infrastructure networks should review the full line of Intel semiconductor and IP products in the light of their cost and power targets to determine how to best take advantage of the full breadth of the unique Intel device offerings. These products help equipment vendors put multiple products with the right bill of materials and the right price point into the market quickly for those with limited R&D budgets. Legal Notices and Disclaimers: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com. 2X Higher Performance or 50% Lower Power based on circuit simulations for the same function performed September 2019. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Performance results are based on testing as of dates shown in configuration details and may not reflect all publicly available security updates. No product or component can be absolutely secure. Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice Revision #20110804 Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
WNC Demos End-to-End 5G O-RAN Solution at MWC Barcelona 2022
As 5G networks proliferate, open and flexible network architectures including Open Radio Area Networks (O-RANs) are clearly becoming the way forward, as evidenced by the fact that O-RAN network architectures have taken center stage at Mobile World Congress (MWC) Barcelona 2022.
Intel Fuels FPGA Innovation with Acceleration Development Platform Strategy
Intel’s development strategy for FPGA-based acceleration cards – powering data centers, networking, and telecommunications – enables rapid development and deployment of production-ready acceleration solutions based on Intel’s latest, fastest, and most powerful FPGAs.Build Better 5G NR Radios with Intel® Agilex™ FPGAs
Intel provides silicon technologies and solutions that address every element in 5G O-RAN architecture, including O-RUs (open radio units), O-DUs (open distributed units), O-CUs (open central units), and O-DRUs (open distributed unit and radio unit combos).Intel’s new technology puts ADCs and DACs operating at 64 Gsamples/sec into packaged FPGAs
Intel has announced new technology that combines FPGA die with high-speed analog chiplets that incorporate both ADCs and DACs operating as fast as 64 Gsamples/sec. With analog sampling rates that fast, this technology represents a revolutionary step towards providing direct RF capability for radar, test & measurement, and wireless communications systems. This heterogeneous system-in-package technology leverages Intel’s Embedded Multi-die Interconnect Bridge (EMIB) and the open standard Advanced Interface Bus (AIB) to seamlessly integrate the ADC/DAC chiplet with the FPGA die. Beamforming systems used in radar and other mission critical applications are currently designed with 32 or more antenna elements sharing a single analog converter. This new architecture significantly increases algorithm complexity and requires substantially more digital signal processing (DSP), memory, and logic FPGA resources. As a result, these systems are now transitioning to wider bandwidth, all-digital designs, where each antenna element connects directly to an ADC and DAC. This all-digital architecture reduces the amount of data transmitted through a system and speeds the transmission of actionable information to enable more rapid decision making by placing required computing resources closer to the sensor. Intel’s state-of-the-art heterogeneous packaging technology can connect chiplets from different processing nodes, including the ADC/DAC chiplet, to the FPGA fabric. This packaging technology connects chiplets using thousands of wires, each operating at 1 Tbps, using EMIB interconnect technology and the AIB physical layer protocol. Combining the high-speed converters with the FPGA in one packaged device eliminates the need for SERDES or JESD204 package-to-package interconnects and significantly reduces power consumption. The first Intel offering to employ this technology will feature an analog data converter with input sample rates up to 64 Gsamples/sec. This offering will combine high-performance ADCs and DACs with a high-density, high-performance FPGA fabric and other dedicated transceiver chiplets in one package. For more information, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Silicom Showcases FPGA SmartNIC Acceleration Cards for O-RAN Apps at MWC Barcelona 2022
Silicom specifically designed the Silicom FPGA SmartNIC N6011 as a 5G O-RAN platform using open Intel® technologies. It is custom designed to meet the real-time processing needs of 5G DUs and can be configured for a wide range of network deployments.We Hope to See You at Intel® FPGA Technology Day 2021
Intel® FPGA Technology Day (IFTD) is a free four-day event that will be hosted virtually across the globe in North America, China, Japan, EMEA, and Asia Pacific from December 6-9, 2021. The theme of IFTD 2021 is “Accelerating a Smart and Connected World.” This virtual event will showcase Intel® FPGAs, SmartNICs, and infrastructure processing units (IPUs) through webinars and demonstrations presented by Intel experts and partners. The sessions are designed to be of value for a wide range of audiences, including Technology Managers, Product Managers, Board Designers, and C-Level Executives. Attendees to this four-day event will learn how Intel’s solutions can solve the toughest design challenges and provide the flexibility to adapt to the needs of today’s rapidly evolving markets. A full schedule of Cloud, Networking, Embedded, and Product Technology sessions, each just 30 minutes long, will enable you to build the best agenda for your needs. Day 1 (December 6), TECHNOLOGY: FPGAs for a Dynamic Data Centric World: Advances in cloud infrastructure, networking, and computing at the edge are accelerating. Flexibility is key to keeping pace with this transforming world. Learn about innovations developed and launched in 2021 along with new Intel FPGA technologies that address key market transitions. Day 2 (December 7), CLOUD AND ENTERPRISE: Data Center Acceleration: The cloud is changing. Disaggregation improves data center performance and scalability but requires new tools to keep things optimized. Intel FPGA smart infrastructure enables smarter applications to make the internet go fast! Day 3 (December 8): EMBEDDED: Transformation at the Edge: As performance and latency continue to dictate compute’s migration to the edge, Intel FPGAs provide the workload consolidation and optimization required with software defined solutions enabled by a vast and growing partner ecosystem. Day 4 (December 9): NETWORKING: 5G – The Need for End-to-End Programmability: The evolution of 5G continues to push the performance-to-power envelop, requiring market leaders to adapt or be replaced. Solutions for 5G and beyond will require scalable and programmable portfolios to meet evolving standards and use cases. To explore the detailed program, see the featured speakers, and register for the North America event, Click Here. Register in other regions below: EMEA China Japan Asia PacificIntel at MWC: Panel Discusses “How is the O-RU reference architecture driving 5G Radio Development?”
Telecom operators need to reduce development time and while implementing new solutions to increase the performance and reliability of 5G networks in a cost-effective manner. Operators have already implemented open systems in their network cores and virtualizing functions, and now they want to achieve the same benefits with RANs including Radio Units (RUs). The Open RU (O-RU) roadmap covers both traditional macro radios and Massive MIMO and addresses key challenges including overall design cost reduction and accelerated time-to-market without sacrificing system-level power and performance. A 30-minute panel discussion about O-RU developments titled “How is the O-RU reference architecture driving 5G Radio Development?” in the Intel® Network & Edge Panel Series discusses the key digital, analog, RF technology, and business considerations that will enable radio ODMs, CMs, and System Integrators to offer flexible and scalable end-to-end RAN solutions. Panel participants include: Tero Kola, VP, System Product Management, Mobile Networks Business Group, Nokia Francisco (Paco) Martin, Group Head of OPEN RAN, Vodafone Rajesh Srinivasa, SVP and GM, Radio Business Unit, Mavenir Mike Fitton, VP, Intel Programmable Solutions Network Business Division, Intel Corporation Nitin Sharma, GM, Wireless Communications, Analog Devices, Inc (ADI) Moderator: Guy Daniels, Director of Content, TelecomTV Interested? Click here to watch the panel discussion. Click here to see all of the panel discussions in the Intel® Network & Edge Panel Series. Click here to see all the Intel events at Mobile World Congress. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Nokia AirFrame Edge Server based on 2nd Gen Intel® Xeon® Scalable CPUs and the Intel® FPGA PAC N3000 suits edge and far-edge cloud RAN, MEC, and 5G deployments
Nokia AirFrame open edge servers feature an ultra-small footprint so they fit well in many locations including existing base station facilities and far-edge sites. These compact servers are provisioned with a real-time, OPNFV compatible, OpenStack distribution that provides both low latency and high throughput for cloud RAN and other applications. The software runs atop integrated 2 nd Generation Intel® Xeon® Scalable CPUs and the optional Intel® FPGA Programmable Acceleration Card (Intel FPGA PAC) N3000, which enhance the server’s capabilities with respect to artificial intelligence (AI) and machine learning (ML) workloads. An optional Fronthaul Gateway module provides 5G/4G/CPRI connectivity to existing legacy radios and contains an L2/L3 switch and an Intel® Stratix® 10 FPGA, which provides high-performance L1 processing. The servers are available in OCP-accepted 2RU or 3RU chassis with as many as five server sled slots and dual redundant AC or DC power supplies. Nokia offers both 1U and 2U server sleds based on 2 nd Generation Intel Xeon Scalable processors with connectivity through front server slots for high accessibility. A new 4-minute Nokia video details the features and benefits of the Nokia AirFrame open edge server for use in a variety of deployments including Cloud RAN, Multi-access Edge Computing (MEC), and 5G. For more technical details about the Nokia AirFrame open edge server, please contact Nokia directly. Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
