Why isn’t the hardware downloadable SOF file of the F-Tile IP design example generated?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, the following F-Tile IP’s design examples do not generate SOF file when the “Targeted Development Kit” is selected as the Intel Agilex® I-Series Transceiver-SoC Development Kit.

• F-Tile CPRI PHY Intel® FPGA IP
• F-Tile CPRI PHY Multirate Intel® FPGA IP
• F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP
• F-Tile Ethernet Intel® FPGA Hard IP
• F-Tile Interlaken Intel® FPGA IP
• F-Tile JESD204B Intel® FPGA IP
• F-Tile JESD204C Intel® FPGA IP
• F-Tile PMA/FEC Direct PHY Intel® FPGA IP
• F-Tile Serial Lite IV Intel® FPGA IP

Resolution

To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, follow the steps below to modify the OPN to "AGIB027R31B1E1VAA."

1. Open design example project file
2. Go to Assignments > Device.
3. Change the device to "AGIB027R31B1E1VAA". Select "No" when asked to remove all location and I/O standard assignments.
4. Launch IP upgrade tool.
5. Use "Auto Upgrade" to complete the IP components upgrade.
6. Proceed to compile the design as usual

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.4.