Why is there a long delay between nCONFIG high and nSTATUS high on the MAX® 10 FPGA devices?

Description

Due to nCONFIG behavior on MAX® 10 FPGA devices, when nCONFIG is held low after the power supply ramp time has completed, you may notice a power-on reset (POR) delay of up to 2.5 ms from nCONFIG high to nSTATUS high.

Resolution

This delay is not seen when nCONFIG is high on power up. Similarly, if a user manually pulls nCONFIG low after the device is in user mode to initiate a reconfiguration, you may notice a power-on reset (POR) delay of up to 2.5 ms from nCONFIG high to nSTATUS high.