Why is the output of Intel® Stratix® 10 CIC Intel® FPGA IP Core for Intel® Quartus® Prime Pro Edition Software version 18.1 software generated example design stuck at 0 in simulation?

Description

Due to a problem with the Intel® Stratix® 10 CIC Intel® FPGA IP in Intel® Quartus® Prime Pro Edition Software version 18.1 software, you may observe the output of this IP stuck at 0 in simulation when the IP is configured with Decimator filter type, and the "Enable variable rate change factor" feature is turned ON.

Resolution

To work around this problem, change the raw data input in cic_ii_0_example_design_tb_input.txt in the test_data directory into the following format:

data1, factor1

data2, factor2

...

For example:

0,8

16,8

...