Why is the jitter performance of the GTS transceiver not optimum when CDR is configured to the Manual LTR mode?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 24.3, you may see that the jitter performance of the GTS transceiver is not optimum when CDR is configured to the Manual LTR mode. 

This is because the default setting for the register “GTS Lane 0 RX CDR VCO Reference Proportional Nominal Gain Value 0x091580[15:12]” is set to 0x3. This register address is shown for Lane 0.

For different lanes, users can refer to the Agilex™ 5 FPGA GTS Transceiver Phy User Guide Section 3.11.3.2. Accessing GTS PMA Registers for different lane addresses for different lanes. 

Resolution

For better jitter improvement in manual LTR mode, it is recommended for the user to change the register “GTS Lane 0 RX CDR VCO Reference Proportional Nominal Gain Value 0x091580[15:12]” to 0xF using the Avalon® memory-mapped interface write. With this, jitter performance can be improved. Note that the address shown is for Lane 0.

For different lanes, users can refer to the Agilex™ 5 FPGA GTS Transceiver Phy User Guide Section 3.11.3.2. Accessing GTS PMA Registers for the change of the different lane address for a different lane.