Why is the Intel® Stratix®10 M20K data corrupted when Simple Dual-Port mode operates with asynchronous read/write clock ECC enabled ECC pipeline register disabled?

Description

Due to incorrect Intel® Quartus® Prime Pro bit setting in Intel® Stratix®10 M20K block when operating with asynchronous read/write clock, ECC enabled ECC pipeline register disabled configuration in Simple Dual-Port mode; you may observe data corruption from Intel® Stratix®10 M20K block. 
Affected Devices: All Intel® Stratix®10 devices
Affected Intel® Quartus® Prime Pro Edition Software versions: Before version 19.2 

Resolution

The issue has been fixed in Intel® Quartus® Prime Pro Edition Software version 19.2.