Why is the E-Tile Hard IP for Ethernet Stratix® 10 FPGA IP 10GE/25GE Design Example Held in Reset?

Description

Due to a problem in the E-tile Hard IP for Ethernet Stratix® 10 FPGA IP 10GE/25GE Example Design, the ethernet circuit is held in reset at startup and the link will not come up.

Resolution

To work around this problem, manually disable the reset by opening the example design in-system sources and probes, and set source bits [3:1] to 3'b111.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition.