Why is the Configuration via Protocol (CvP) periphery image configuration time exceeding the PCIe 100 ms power-up-to-active time requirement?

Description

In Intel® Quartus® Prime Pro Edition Software version 21.2, the CvP PCIe link might not be able to enumerate properly with Intel Agilex® 7 devices. This is because the periphery image configuration time exceeds the PCIe 100 ms power-up-to-active time requirement.

Resolution

To work around this problem, re-enumerate the PCIe link once the FPGA is successfully configured.

This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 21.3.