Knowledge Base Article
Why is output always disabled when the first output enable register is ON while the first output register is OFF in the Arria® 10 FPGA device?
Description
Due to a limitation of the Quartus® Prime Pro Edition Software, output may always be disabled regardless of the output enable signal when the fast output enable register is ON while the output register is OFF in the Arria® 10 FPGA device. See the following condition list for details.
- Fast output register = OFF, Fast output enable register = OFF : OK
- Fast output register = ON, Fast output enable register = ON : OK
- Fast output register = OFF, Fast output enable register = ON : Fail
- Fast output register = ON, Fast output enable register = OFF : OK
Although the Quartus® Prime Pro Edition Software does not expect this usage, no error or warning is issued.
Resolution
Use conditions 1, 2, or 4 in the description to avoid this limitation.
To ensure conditions 1, 2, or 4, you can intentionally set the fast output register and fast output enable register to ON or OFF using the following assignment.
set_instance_assignment -name FAST_OUTPUT_REGISTER <ON/OFF> -to <pin name>
set_instance_assignment -name FAST_OUTPUT_ENALBE_REGISTER <ON/OFF> -to <pin name>
A future version of the Quartus® Prime Pro Edition Software will issue an error when there is a case where the first output enable register is ON while the output register is OFF.