Why is my PCIe Slot Clock Configuration bit always set to 1 regardless of the GUI selection?

Description

Due to a problem with the Altera® Stratix® V Hard IP for PCI Express*, the hardware Slot Clock Configuration bit (Link Status Register[12]) will always be set to 1 in the PCIe* Configuration Space regardless of the "Slot Clock Configuration" setting in the PCIe Capabilities Link tab of the GUI. This problem occurs in both simulation and hardware. 

Resolution

To work around this problem, edit the altpcie_hip_256_pipen1b.v file in the \synthesis\submodules directory as follow.

1) at around line 0088 add  -->   parameter slotclk_cfg = "dynamic_slotclkcfg",
2) at around line 2699 add  -->   .slotclk_cfg(slotclk_cfg),

This problem is fixed starting in Intel® Quartus® Prime Standard Edition software release v17.0.