Why is link up error seen in simulation using either the F-Tile Ethernet Intel® FPGA Hard IP or the F-Tile Ethernet Multirate Intel® FPGA IP when FAST SIM switches with UX_CLOCK_DRIFT_CORRECTION macro is enabled?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and earlier, you may see a link-up error in simulation using either the F-Tile Ethernet Hard IP or the F-Tile Ethernet Multirate IP when FAST SIM switches with the UX_CLOCK_DRIFT_CORRECTION macro is enabled.

Resolution

The workaround for this problem is the removal of FAST SIM switches with the UX_CLOCK_DRIFT_CORRECTION macro from the design. 

This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.2.