Why doesn't the Intel® Arria® 10 PCI* Express HIP set pattern lock bit when receiving modified compliance pattern at LTSSM=Polling Compliance state?

Description

According to PCIe* specification, when the LTSSM of PCIe* Root Port or Endpoint is in the polling compliance state, the pattern lock bit in transmitted data should be set when it receives a modified compliance pattern and locks to the modified compliance pattern.

Intel® Arria® 10 PCIe* Hard IP has a problem: it will never lock to the modified compliance pattern. Intel Arria 10 PCIe* Hard IP is expecting data pattern 4A_BC_B5_BC { D10.2, K28.5, D21.5, K28.5 } to be one of the following sequence:

1. BC_4A_B5_BC { K28.5, D10.2, D21.5, K28.5 }
2. BC_BC_4A_B5 { K28.5, K28.5, D10.2, D21.5 }
3. B5_BC_BC_4A { D21.5, K28.5, K28.5, D10.2 }
4. 4A_B5_BC_BC { D10.2, D21.5, K28.5, K28.5 }

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.1.