Why does the Triple-Speed Ethernet FPGA IP for Agilex™ 5 FPGA devices, when configured with the 'Transceiver type' set to 'LVDS I/O', result in a fitter error for the Quartus® Prime Pro Edition software version 24.3.1?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1, when compiling the design, you may see a fitter error indicating that the fitter cannot place 1 BYTE because there is no routing connectivity between the BYTE and the destination pin.

This problem occurs because the IP submodule Agilex™ 5 LVDS SERDES IP requires specific pin parameter settings based on the intended pin lock. However, these settings are not currently exposed through the Triple-Speed Ethernet IP GUI for the Agilex™ 5 FPGA devices, which prevents the Quartus® Prime software from correctly routing the signals to the designated I/O pins.

Resolution

A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.3.1.
Download and install patch 1.18 from the link below.

For Quartus® Prime Pro Edition software version 24.3.1

• Download patch 1.18 for Windows (quartus-24.3.1-1.18-windows.exe)
• Download patch 1.18 for Linux (quartus-24.3.1-1.18-linux.run)
• Download the Readme for patch 1.18 (quartus-24.3.1-1.18-readme.txt)

Please follow the User guide instructions for updating the PIN parameter settings.
Please contact your local Sales representative or submit a request through the Support page for further support.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.