Why does the TimeQuest timing analyzer report eight additional generated clocks for the Altera_PLL megafunction in addition to those I am using?

Description

For designs using the Altera_PLL megafunction, the TimeQuest timing analyzer Report Clocks task displays eight additional clocks in addition to those used in your design. These clocks represent the eight taps of the VCO of the PLL and are reported for all fracturable PLLs. Device families that use the ALTPLL megafunction do not have fracturable PLLs and do not report these additional clocks. The eight additional clocks have the following clock naming convention:

<pll name>|fpll|vcoph[0..7]