Why does the Soft LVDS RX Intel® FPGA IP with external PLL option not function correctly in Intel® MAX® 10 devices when using the Quartus® II software version 14.1?

Description

Due to a known problem in the Quartus® II software version 14.1, the Soft LVDS RX Intel® FPGA IP in external PLL mode, may not function correctly in Intel® MAX® 10 devices.

This is because the rx_syncclock and rx_readclock ports are missing from the Intel MAX 10 FPGA Soft LVDS Intel FPGA IP, which will cause the rx_out parallel data to exhibit stuck data.

Resolution

To work around this problem, change the Soft LVDS RX Intel FPGA IP to internal PLL mode.

This problem is scheduled to be fixed in a future release of the Intel Quartus software.