Why does the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express design example use the CML I/O standard on the PCI Express reference clock input pins?

Description

Due to a problem in the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express design example, the default I/O standard for the PCI Express reference clock input pins is CML.

Resolution

According to the PCI Express Base Specification and the Intel Agilex® Device Family Pin Connection Guidelines, the reference clock input pins should be set to HCSL I/O standard.

This problem is fixed in Intel® Quartus® Prime Pro Edition Software 21.3. 

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Error (12341): The input pin has a HCSL I/O standard, but the selected device does not support input pin operation with a HCSL I/O standard.