Why does the Quartus® Prime Pro Edition Software report errors when the F-Tile Triple-Speed Ethernet FPGA IP is configured with LVDS I/O as the transceiver type for the Agilex™ 7 FPGA M-Series devices?

Description

Due to a limitation of the F-Tile Triple-Speed Ethernet FPGA IP, when the F-Tile Triple-Speed Ethernet FPGA IP is configured with LVDS I/O as the Transceiver type for the Agilex™ 7 FPGA M-Series devices, the Quartus® Prime Pro Edition Software will report errors.

Resolution

This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.1

Additional Information

This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.1