Why does the P-tile Avalon® Streaming FPGA IP for PCI Express* show an RDC-50002 warning?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 21.4 and later,  you might see the following Design Assistant rule violation for the P-tile Avalon® Streaming FPGA IP for PCI Express* 

• RDC-50002 - Reconvergence of Multiple Asynchronous Reset Synchronizers in a Common Reset Domain

Resolution

This violation is safe to ignore.

To waive the warning, copy the da_drc.dawf file from the P-tile Avalon® Streaming FPGA IP for PCI Express* PIO example design add it to the project's folder and recompile.