Why does the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express design example targeting the Intel Agilex® 7 FPGA show minimum pulse width violations?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2 and earlier, you might see minimum pulse width violations when using the design example for the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express targeting the Intel Agilex® 7 FPGA.

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Edition Software 21.3.