Why does the Intel® Arria® 10 FPGA RapidIO I and II IP Cores Generate Testbench result in error for input port connections?

Description

The RapidIO I and II user guide recommends using the working example functional simulation testbench that is generated when IP simulation model is generated. However, custers who would like to create their own testbench can use the "Generate Testbench System" option in the Platform Designer.

During the Platform Designer generation, the following error will be seen:

"Error: <qsys system>_tb.<qsys system>_inst.tx_bonding_clocks_ch0: <qsys system>_inst.tx_bonding_clocks_ch0 must be connected to a hssi_bonded_clock output"

Resolution

This error is expected. The Native PHY requires the tx_bonding_clock input port be connected to a Transceiver phase-locked loop (PLL) output clock. The Generate Testbench simply creates a dummy wrapper to the IP core and hence the error informs the user that ports need to be connected later in the final design.

To work around this problem, follow these steps:

1. Close the Generation dialog box.
2. In the Intel® Quartus® Prime Software, go to File > Open > <qsys system>_tb > <qsys system>_tb.qsys 
   You will get an error message on the unconnected tx_bonding_clocks.
3. Export the tx_bonding_clocks ports to resolve the error.
4. Go to Generate > Generate HDL... > Simulation > select intended Create simulation  model > Generate.
5. Done. You will get the same simulation model from the Generate testbench system.

This problem is not scheduled to be fixed in a future release of the Intel Quartus Prime Software.