Why does the F-Tile HDMI IP Design Example in AXIS-VVP Without Frame Buffer mode fail to output at certain resolutions (4k60 and above) on the Agilex™ 7 FPGA?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, the F-Tile HDMI IP Design Example in AXIS-VVP Without Frame Buffer mode will fail to output certain resolutions (for example, 4k60 and above) for the Agilex™ 7 FPGA devices.

Resolution

To work around this problem, use the F-Tile HDMI IP Design Example in AXIS-VVP with Frame Buffer TMDS mode when targeting 4k60 resolution and above.

This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition Software.