Why does the F-Tile HDMI IP Design Example fail to program on the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, the F-Tile HDMI IP Design Example will fail to program on the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit.

This problem is due to an incorrect board setting in the Device & Pin Option -> Power Management & VID tab.

Resolution

To resolve this problem, please refer to the Add SmartVID Settings in the Quartus® Prime QSF File for the correct board settings to be used in the Power Management & VID tab and update manually before compiling the design.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.