Why does the F-Tile Ethernet FPGA Hard IP fail the Quartus® Prime Pro Edition - Support Logic Generation stage when upgrading a design from the Quartus® Prime Pro Edition Software version 23.1 to version 23.2 in the Windows* OS?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, upgrading a version 23.1 design that includes the F-Tile Ethernet FPGA Hard IP where the “Use source address insertion” GUI parameter has been set will cause a “Support Logic Generation” failure in the Windows* OS.

Resolution

To work around this problem in the Quartus® Prime Pro Edition Software version 23.2 software, perform the following steps:

1. In your 23.1 project, locate the “bb_f_ehip_mac_txmac_saddr” parameter in the <ethernet variant name>/synth/<ethernet_variant_name>.v file
2. In your 23.2 project, locate the “bb_f_ehip_mac_txmac_saddr” parameter in the <ethernet variant name>/synth/<ethernet_variant_name>.v file
3. Copy the value for the 23.1 “bb_f_ehip_mac_txmac_saddr” parameter into the value of the 23.2 “bb_f_ehip_mac_txmac_saddr” parameter.
4. Save the 23.2 <ethernet variant name>/synth/<ethernet_variant_name>.v file
5. Recompile the Quartus® Prime Pro Edition Software version 23.2 project

Alternatively, generate a clean from scratch version of the F-Tile Ethernet FPGA Hard IP in the Quartus® Prime Pro Edition Software version 23.2.

This problem has been fixed in version 23.3 of the Quartus® Prime Pro Edition Software.