Why does the example design for Stratix® 10 10GBASE-KR PHY IP generated using the Quartus® Prime Pro Edition software version 24.3 and run in Questa*-Intel® FPGA or Starter Edition fail during simulation?

Description

Due to a problem in the Stratix® 10 10GBASE-KR PHY IP example design generated using the Quartus® Prime Pro Edition software version 24.3, the simulation fails for the  Questa*-Intel® FPGA or Starter Edition simulators.

Resolution

To work around this problem, make the following changes in the testbench.v, testbench related file.

1) Add the following line, 

parameter SIM_TIMEOUT = 64'd5000000000;

2) At Line 225 (before the change#1), 

for (cycle = 1; cycle <= 1; cycle = cycle + 1) begin

Change to:

for (cycle = 1; cycle <= 6; cycle = cycle + 1) begin

3) Lines 323 to 328 (before the change#1)

///// 2.0ms timeout    
initial begin
#2_000_000_000; //ms
$display ("Test did not finish. Timing out at 2ms"); 
$finish();
end

Change to: 

///// 5.0ms timeout    
initial begin
#SIM_TIMEOUT ;

$display ("Test did not finish. Timing out at 5ms"); 
$finish();
end

This issue will be fixed in a future version of the Quartus® Prime Pro Edition Design Software.