Why does the Debug Toolkit for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* and the R-Tile Intel® FPGA Compute Express Link (CXL) IP fail upon opening after an FPGA reconfiguration?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.2 and earlier, you may observe the below error when opening the Debug Toolkit for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* and the R-Tile Intel® FPGA Compute Express Link (CXL) IP after using the Debug Toolkit and then performing an FPGA reconfiguration.

 

master_read_32: This transaction did not complete in 60 seconds.  System Console is giving up

 

 

 

 

Resolution

To work around this problem, perform a FPGA power cycle after using the Debug Toolkit, prior to performing an FPGA reconfiguration.

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 23.3.