Why does Quartus® Prime Pro compilation fail with error 23051 after upgrading the F-Tile HDMI IP Design Example to 25.1.1?

Description

The F-Tile HDMI Altera® Design Example in Quartus® Prime Pro Edition Software 25.1.1 compilation fails at the Logic Generation stage, and Quartus® reports an error of the following form: 

Error(23051): NIOS data memory size 1024KBytes of Dynamic Reconfiguration Controller IP agx_hdmi21_frl_axi_demo/u_nios/dr_f/nios_dr_f is smaller than required MIF Size of 1141464Bytes to store the data in NIOS Memory 

This error also occurs after upgrading the F-Tile HDMI Altera® Design Example from previous versions.

This is due to a significant memory increase in the MIF size required by the F-Tile Dynamic Reconfiguration (DR) IP. 

Resolution

Increase the DR memory size in Quartus® Prime Pro Edition Software 25.1.1 to overcome the compilation error. A new memory size option is introduced in the Nios® data memory size within the Dynamic Reconfiguration IP GUI, which allows memory size selection up to 2048kB.

i.e., double the maximum amount of memory previously. In the HDMI Design in Quartus, under Project Navigator, navigate to the IP Components tab and open nios_dr_f to launch the F-Tile Dynamic Reconfiguration Suite IP GUI. 

In the Dynamic Reconfiguration Controller IP tab ➤ Select NIOS data memory size option as 2048KBytes. Regenerate the DR IP by clicking on Generate HDL to regenerate the HDL files required. Recompile the design. 

#NOTE There will be an increase in M20K memory blocks in your chosen device when choosing this option

Additional Information

This issue will be fixed in Quartus® Prime Pro Edition Software version 25.3