Why does PFL-II IP not meet Agilex™ 7 'nCONFIG high to nSTATUS high' timing specifications for FPGA configuration?

Description

Due to a problem in Quartus® Prime Pro Edition Software version 20.1, the PFL-II IP times out at 5ms. The expected maximum configuration time from the datasheet is 20ms for Agilex™ 7.

Resolution

To work around this, the user can change the IP top-level parameter called ‘CONF_WAIT_TIMER_WIDTH’ by adding +2.

 

This issue has been fixed in the Quartus® Prime Pro Edition Software version 23.2.