Why does my RAM attribute “no_rw_check” getting ignored in Intel® Quartus® Prime software version 16.0 onwards?

Description

Due to a problem in the Intel® Quartus® Prime software version 16.0 and later, you may see that the attribute of 'no_rw_check' is ignored if you declare the output of the RAM to an intermediate signal instead of output port. This problem does not occur in the Intel Quartus Prime software version 15.1 and earlier.

If you have a design migrated to the version of the Intel Quartus Prime software 16.0 and later, check the report under analysis and synthesis -> LPM_Parameter Settings -> RAM. Make sure that the parameter READ_DURING_WRITE_MODE_MIXED_PORTS has a value of DON’T CARE if 'no_rw_check' attribute is used. 

Example below show the none detected attribute 'no_rw_check' code in the Intel Quartus Prime software version 16.0 onwards:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY ram IS

PORT (

clock: IN STD_LOGIC;

data: IN STD_LOGIC_VECTOR (2 DOWNTO 0);

write_address: IN INTEGER RANGE 0 to 31;

read_address: IN INTEGER RANGE 0 to 31;

we: IN STD_LOGIC;

q: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)

);

END ram;

ARCHITECTURE rtl OF ram IS

TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL ram_block: MEM;

ATTRIBUTE ramstyle : string;

ATTRIBUTE ramstyle of ram_block : signal is "no_rw_check";

SIGNAL read_address_reg: INTEGER RANGE 0 to 31;

SIGNAL q_reg : STD_LOGIC_VECTOR (2 DOWNTO 0);

BEGIN

PROCESS (clock)

BEGIN

IF (clock'event AND clock = '1') THEN

IF (we = '1') THEN

ram_block(write_address) <= data;

END IF;

read_address_reg <= read_address;

END IF;

// not detected attribute 'no_rw_check' snipped code in Intel Quartus Prime software version 16.0 onwards

------------------------------------------------------------------------------------

IF (clock'event AND clock = '1') THEN

q_reg <= ram_block(read_address_reg);

END IF;

q <= q_reg;

------------------------------------------------------------------------------------

END PROCESS;

END rtl;

Resolution

To work around this problem, turn on the Add Pass-Through Logic to Inferred RAMs in the

Assignment -> settings -> compiler settings -> advance settings (synthesis)

Or

Declare the output signal of the RAM as output port without using intermediate signal, by replacing the above snipped code with the code below:

------------------------------------------------------------------------------------

IF (clock'event AND clock = '1') THEN

q <= ram_block(read_address_reg);

END IF;

------------------------------------------------------------------------------------

This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro edition software.