Why does my F-Tile Ethernet Intel® FPGA Hard IP Design Example 40GE-4 variant fail to pass simulation with a System PLL frequency above 805.664062MHz?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, the F-Tile Ethernet Intel® FPGA Hard IP Design Example 40GE-4 variant will fail to pass simulation when using a System PLL with a frequency above 805.664062MHz.

Resolution

To work around this problem, choose a System PLL frequency of 805.664062MHz.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.