Why does MAX® 10 FPGA PFL flash_nreset behave like an open-drain output when the Fitter report shows Open Drain = No?

Description

In Quartus® Prime Standard Edition Software version 21.1, the flash_nreset output may appear to behave as an open-drain signal even when the Quartus Fitter report shows Open Drain = No for design targeting MAX® 10 FPGA using the Parallel Flash Loader (PFL) IP.

When the PFL option Set flash bus pins to tri-state when not in use is enabled, the flash_nreset signal is driven low when asserted and placed in high impedance (Z) when de-asserted. In this condition, an external pull-up is required for the pin to reach a logic-high level.

The Fitter report can still show Open Drain = No because it is reporting whether the dedicated open-drain hardware feature is used, not whether the resulting pin behavior is electrically equivalent to open-drain operation.

Resolution

This is expected behavior and is not a Quartus or PFL defect.

The apparent discrepancy is caused by interpreting the Fitter report's Open Drain field as a description of the pin's logical/electrical behavior. The field indicates whether the dedicated open-drain hardware feature is used. It does not by itself indicate whether the RTL creates a low/high-impedance output that behaves similarly to open-drain operation.