Why does an error occur when the MDIO:MDIO and MDIO:MDC signals are assigned to the HPS dedicated I/O pins in Platform Designer?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, Platform Designer fails to generate HDL if you are assigning the MDIO0 signals to HPS_IOB_11 and HPS_IOB_12.   The figures below show the pin assignment and the error generated.

 

 

 

 

 

Resolution

There are no issues if the MDIO0 signals are assigned to HPS_IOA_11/HPS_IOA_12 or HPS_IOB_23/HPS_IOB_24.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.