Why do the R-Tile Avalon® Streaming FPGA IP for PCI Express* Configuration Intercept Interface (CII) parameters change from Enabled to Disabled after upgrading to Quartus® Prime Pro Edition version 25.1.1?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, the error message shown below may be seen after upgrading the R-Tile Avalon® Streaming FPGA IP for PCI Express*, if the design has logic connected to the Configuration Intercept Interface (CII):

Error (13305): Verilog HDL error at <ip_variation_name>.sv(*): can't find port "p*_cii_*"
 

Resolution

To work around this problem in the Quartus® Prime Pro Edition software version 25.1.1, open the R-Tile Avalon® Streaming FPGA IP for PCI Express* IP Parameter Editor (GUI) and manually re-enable the Configuration Intercept Interface (CII) parameters in the PCIe Avalon Setting Tab for each bifurcation port.

This problem has been fixed in version 25.3 of the Quartus® Prime Pro Edition software.