Why do the Intel® MAX® 10 FPGA pin numbers K22 and K21 on the Intel® MAX® 10 FPGA 10M50 Evaluation Kit not support the LVDS IO standard?

Description

Due to a known problem with the MAX 10® FPGA 10M50 Evaluation Kit,  it is incorrectly stated that the Intel® MAX® 10 FPGA pin numbers K22 and K21 can be used as differential clock inputs. 

However, these pins cannot be used as differential clock inputs. 

Resolution

 This information will be corrected in a future version of the Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide.