Why do the 10G and 25G example design SOF files generated for the E-tile Ethernet IP for Agilex™ 7 FPGAs with target development kit "Agilex™ 7 FPGA F-series Development Kit (Production 1 P-Tiles & E-tile)" fail to program?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, you may see failures when programming SOF files generated with the 10G and 25G E-Tile Ethernet Hard IP design examples for Agilex™ 7 FPGA devices.

This issue applies to the E-Tile Ethernet Hard IP for Agilex™ 7 FPGA devices and is limited to the 10G and 25G Example Designs

Resolution

To workaround this problem, modify the PWRMGT_LINEAR_FORMAT_N setting to "-13" in the hardware test design QSF file located in <design_example_dir>/hardware_test_design.

This problem is planned to be fixed in future versions of the Quartus® Prime Pro Software Edition.