Why do I see recovery timing violations within the Altera POS-PHY Level 4 MegaCore in my design?

Description

Due to a problem with the auto generated synopsys design constraints (.sdc) file for the Altera® POS-PHY Level 4 (Receiver) MegaCore®, you may see recovery timing violations on paths from "*dpa_align:dpa_align|dpa_reset" to "*altlvds_rx_component|*auto_generated|rx*bit_slip_reg".

This is due to the following auto generated .sdc assignments being ignored:

set_multicycle_path -setup -end -from "*dpa_align:dpa_align|dpa_reset" -to "*altlvds_rx_component|*auto_generated|rx[*]~bit_slip_reg" 2
set_multicycle_path -hold  -end -from "*dpa_align:dpa_align|dpa_reset" -to "*altlvds_rx_component|*auto_generated|rx[*]~bit_slip_reg" 1

To workaround this problem, you can replace the assignments above (which can be found in the auto generated .sdc file) with the following assignments:

set_multicycle_path -setup -end -from [get_keepers {*dpa_align:dpa_align|dpa_reset}] -to [get_keepers {*altlvds_rx_component|*auto_generated|rx*~bit_slip_reg}] 2
set_multicycle_path -hold  -end -from [get_keepers {*dpa_align:dpa_align|dpa_reset}] -to [get_keepers {*altlvds_rx_component|*auto_generated|rx*~bit_slip_reg}] 1

This problem is scheduled to be resolved in a future release of the Altera Complete Design Suite.