Why do I see error about Number of Clock Outputs exceeding 64 outputs when I use Configuration Clock Endpoint to Debug Logic IP in my Agilex™ 5 FPGA design?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.1 and earlier, if you instantiate more than 64 Configuration Clock Endpoint to Debug Logic IP in your design, you will see an error during Analysis and Elaboration Stage:

Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.clockfabric: "Number of Clock Outputs" (NUM_CLOCK_OUTPUTS) 109 is out of range: 1-64

Resolution

Reduce the number of configuration clock endpoints to 64 or less in your design.

This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.1.1.