Why do I see an error accessing my FPGA IP on my Intel® Arria® 10 SoC Design?

Description

In the Arria® 10 U-Boot bootloader in SoC EDS version 15.1.2 and earlier, there is a NOC timeout that is erroneously left enabled by the reset_assert_all_bridges function. This timeout can be reached if the IP in the FPGA is slow to respond, resulting in an access error.

Resolution

This problem is scheduled to be fixed in the next release of SOC EDS. There is a patch available to address this issue with previous releases here:  https://github.com/altera-opensource/u-boot-socfpga