Why do I get a fitter error when enabling Intel Agilex® 7 FPGA Scheme 2 DDR4 IP in DIMM with 2 ranks in Intel® Quartus® Prime Pro Edition Software version 23.3?

Description

To enable Intel Agilex® 7 FPGA Scheme 2 DDR4 IP in DIMM with 2 ranks in Intel® Quartus® Prime Pro Edition Software version 23.3, we require CK clocks
"Force Ranks to share One Memory Interface Clock" = True
"Alert_N Pin Placement" = Alert_N in AC2
"Minimum Number of AC Lanes for DDR4" = 3

Resolution

This issue is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 23.4