Why are there timing violations within my PLL Reconfig Intel® FPGA IP?

Description

The maximum frequency for the mgmt_clk and scanclk reconfiguration clock inputs for PLL reconfiguration are specified in the respective device datasheets for Stratix® V, Arria® V, and Cyclone® V devices with the symbol t_DYCONFIGCLK.

Resolution

The PLL Reconfig Intel® FPGA IP might require a lower clock frequency to achieve timing closure.  You should use the Timing Analyzer to ensure that your choice of clock frequency for mgmt_clk and/or scanclk will meet the timing requirements of your chosen device.