Why are the micro-parameters, uTsu, uTh and uTco zero in the timing report of Altera’s 28nm FPGA?

Description

The micro-parameters are generally set to zero intentionally for Stratix® V, Arria® V and Cyclone® V device families except for those of the LAB.  In these device families, the delays that were previously represented in those parameters are accounted for in the "To" or "From" register delays.