When using Partial Reconfiguration are the PR_DONE, PR_READY, PR_ERROR, and PR_REQUEST pins powered by VCCPGM or VCCIO?

Description

When using Partial Reconfiguration (PR) the PR_DONE, PR_READY, PR_ERROR, and PR_REQUEST pins will be powered by VCCIO as PR operates in usermode with the device still running while the PR region is being frozen.

Are the Partial Reconfiguration output pins on Stratix V, Arria V and Cyclone V devices configured as Open Drain by default, when these pins are enabled in my Quartus II project?

Updated 3 months ago

Version 3.0

arria® v fpgas and socs

cyclone® v fpgas and socs

stratix® v fpgas

troubleshooting

Knowledge Base Article

When using Partial Reconfiguration are the PR_DONE, PR_READY, PR_ERROR, and PR_REQUEST pins powered by VCCPGM or VCCIO?

Description

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