When the Analog to Digital Converter (ADC) is enabled, why does the generated .pin file report incorrect voltage for banks 1A and 1B on MAX® 10 FPGA?

Description

The generated .pin file will display the default voltage settings for IO banks 1A and 1B unless the voltage values for these banks are manually changed.

When using the Analog to Digital Converter on a MAX® 10 FPGA with a single core power supply, IO banks 1A and 1B will be tied to VCC_ONE, which has a value of 3.0V or 3.3V. However, this is not done automatically by Quartus® Prime Standard Edition Software and must be updated to the value of the two IO banks by the user. 

Resolution

To fix this problem, manually set the voltage value of IO banks 1A and 1B.

The voltage can be set in two different ways.

1. Through the .qsf file, by adding the following lines:

set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1A

set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1B

2. With the Quartus® Prime Pin Planner GUI