What is the status of the General Purpose I/O pins during Configuration via Protocol(CvP) Init or CvP Update?

Description

When performing CvP Init, once the periphery file is loaded, only the Hard IP for PCI Express is released from reset.  All other GPIOs are released after the core is loaded. Consequently, all other I/Os are tristated until core configuration is complete.

 

Similarly, during CvP Update, the GPIOs are tristated during the update process, and are re-released after the updated core is loaded. The same is true for reserved pin assignments. These assignments are not active until the core is loaded.

 

There is no way in Quartus® II software to make I/Os stay at a specific value during CvP Init or Update. Pull-up or pull-down resistors are required on the PCB if specific values are required during the CvP process.