What is the earliest stage of compilation that I can generate a timing netlist?

Description

If you are using the Intel® Quartus® Prime Pro Edition software you can create a timing netlist after the fitter plan stage, if you are using the Intel® Quartus® Prime Standard Edition software you can create a timing netlist after the analysis and synthesis stage.

In the Intel Quartus Prime Standard Edition software, use this command to generate the timing netlist:

create_timing_netlist -post_map