TimeQuest May Incorrectly Report Timing Failure for Hard Memory Interface on HPS Subsystem for Cyclone V SoC Devices

Description

This problem affects DDR2, DDR3, and LPDDR2 products.

For the hard memory interface using the ARM processor on Cyclone V SoC devices, Report DDR in TimeQuest may report erroneous timing failures. Such reports of timing failure in postamble timing analysis or DQS vs CK timing analysis can be ignored.

This issue does not apply to hard or soft memory interfaces in the FPGA.

Resolution

The workaround for this issue is to ignore the reported timing failure.

This issue will be fixed in a future release.