Node: <hierarchy>|gen_ct1_hssi_pldadapt_rx.inst_ct1_hssi_pldadapt_rx~aib_rx_internal_div.reg was determined to be a clock but was found without an associated clock assignment.

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 17.1 and earlier, you might encounter this warning during timing analysis when instantiating multiple instances of the Transceiver Native PHY Intel® Stratix® 10 FPGA IP in your design.

The problem is specific to cases where the Transceiver Native PHY Intel® Stratix® 10 FPGA IP instance names includes square brackets contaning more than one digit.

For example:

"my_instance[0].u0" would work fine.

"my_instance[10].u0" would result in the error

Instance names containing square brackets are a common result of using generate statements to instantiate multiple instances of the same component.

Resolution

To work around this problem, ensure that your Transceiver Native PHY Intel® Stratix® 10 FPGA IP instance names do not include square brackets containing more than one digit.

This problem is scheduled to be resolved in a future release of the Intel Quartus Prime Pro Edition Software.