In Qsys, why are the Triple Speed Ethernet(TSE) clock names for Intel® Arria® 10 not described in the User Guide?

Description

The TSE User Guide describes the clock names used in the IP Catalog flow for devices released before Intel® Arria® 10.

Resolution

The following Qsys clock names are equivalent to the documented clock names:

control_port_clock_connection = clk
receive_clock_connection = ff_rx_clk
transmit_clock_connection = ff_tx_clk
pcs_ref_clk_clock_connection = ref_clk
tx_serial_clk = comes for the external TXPLL
rx_cdr_refclk = ref_clk

In Intel® Arria® 10, the TX PLL is external to the TSE IP and must be manually generated and connected by user RTL. You must configure the Intel® Arria®10 Transceiver ATX PLL with an output clock frequency of 1250.0 MHz.

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