How is the PLL Fractional Divider value calculated by the Quartus II software when using the Altera PLL megafunction?

Description

The attached document describes how the Quartus® II software calculates the PLL Fractional Divison parameter, when using the Altera® PLL megafunction in fractional mode, and how you can enter this value in the Altera PLL megafunction.

How precise are the output clock frequencies generated by the Altera_PLL megafunction?
What is the purpose of the Channel Spacing field, when implementing a fractional PLL in the Altera PLL megafunction?

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How is the PLL Fractional Divider value calculated by the Quartus II software when using the Altera PLL megafunction?

Description

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