How do non-posted tag requests work in the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCI Express* core when more than one Physical Function is enabled?

Description

When using the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCI Express* core with more than one Physical Function enabled, the pool of tags for non-posted requests is shared across all the enabled Physical Functions.

Resolution

This additional information is scheduled to be added in a future update to the user guide.